In-circuit testing is used to test integrated circuit devices to ensure, among other things, that the various components of a particular device under test (DUT) are properly interconnected. In addition, in-circuit testing techniques are used to ensure that the various integrated circuit devices mounted together on a common circuit board are properly interconnected. The primary advantage of in-circuit testing is that the DUT can be tested without physically disconnecting it from its surrounding circuitry. This translates into significant savings in both time and cost.
The Institute of Electrical and Electronic Engineers (IEEE) boundary-scan standard specifies test logic that can be incorporated into an integrated circuit device to provide standardized approaches to testing the device using in-circuit testing techniques. See IEEE standard 1149.1. This standard is fully described in the document entitled "IEEE Standard Test Access Port and Boundary-Scan Architecture," published by the IEEE, which is incorporated herein by reference. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principles.
FIG. 1 illustrates an exemplary implementation for a boundary-scan cell 10 that could be used for an input or output terminal of an integrated circuit. Depending upon the control signals "M" and "S/L", applied to the multiplexers 12A, 12B, data can either be loaded into the scan register from the "SI" port, or driven from the register through the "SO" port of the cell into the core integrated circuit of the component. The operation of this boundary-scan cell is more fully described in the above-referenced IEEE standard document.
FIG. 2 illustrates how a number of boundary-scan cells 10A, 10B, 10C, etc., may be interconnected to each other and to a core integrated circuit 18, to form a "boundary-scan device" 16, i.e., a device equipped with boundary-scan test capability, as defined by the above-referenced IEEE standard. As shown in FIG. 2, the boundary-scan cells for the pins of a component 16 are interconnected so as to form a shift-register chain around the border of the integrated circuit 18, and this chain is provided with serial input and output connections "TDI", "TDO" and appropriate clock and control signals (not shown).
To allow the components to be tested, the boundary-scan register can be used as a means of isolating on-chip system logic from stimuli received from surrounding components while an internal self-test is performed. Alternatively, if the boundary-scan register is suitably designed, it can permit a limited slow-speed status test of the on-chip system logic since it allows delivery of test data to the component and examination of the test results.
Note also that by parallel loading the cells at both the inputs and outputs of a component and shifting out the results, the boundary-scan register provides a means of observing the data flowing into the component through its input pins and a means of delivering data from the component through its output pins. This mode of operation is valuable for fault diagnosis since it permits examination of connections not normally accessible to the test system, e.g., the connection (i.e., trace) between an external input terminal 11A of the device and an input 18A to the core integrated circuit 18.
The precise sequence of signals that needs to be input to these TAP (Test Access Port) inputs is unimportant as far as the present invention is concerned. It is important to note, however, that during various types of testing it is often necessary to drive and receive data to/from both the parallel inputs to these shift registers and to/from the TDI/TDO terminals. For example, as alluded to above, this is necessary during an important test called a connect test, i.e., a verification that all of the internal input and output terminals of the chip are properly connected to the board.
In order to perform the connect test, certain signals must be presented to the board nets via test drivers, certain signals must be received from the board via test receivers, certain signals must be driven to TDI and the various control ports of the scan cells 10A, 10B, etc., from test drivers, and certain signals must be received via TDO by the test receivers. A problem with this testing procedure is that data from all of the test receivers is strobed in at the same time. This parallel input is called an "input vector" and it represents a sample of activity from some group of board nets at a particular point in time. Now, in order to detect and diagnose a fault in the device, it is necessary to analyze all of the data from a given point in time at once. If a failure is detected at some point, the test is halted and the failure analysis printed.
However, in the case of a boundary scan device, while the parallel data inputs to a device may all be sampled at the same time as the parallel tester inputs (i.e. the data outputs of the device), the input data to the core integrated circuit 18, sampled by the scan cells, is not available to the tester until additional control vectors have been input to the TAP to shift out this information. Therefore, if a fault is detected at some tester input, the information necessary for a complete fault analysis is not available at that time. The data captured by the respective scan cells must be clocked out and this serialized data lined up with the appropriate parallel data taken from the tester inputs. This is difficult to do with known test receivers since they are not designed to store serial data.
Accordingly, the object of the present invention is to provide a method and apparatus by which a test comparator (receiver) can be connected to a storage-device and this data then re-formatted so that all information from both the parallel tester inputs and the boundary-scan cells may be simultaneously analyzed to isolate faults in the DUT.